Graduate Thesis Work

Erithacus Digital Communications System

I'm currently working on the design and implementation of a digital communications testbed for use in the University's digital communications labs. The need for students to vary certain parameters of a communications system to measure performance brings out many interesting problems in the design of such a system.

Two questions present themselves: 1. Will this ever be used? and 2. What's my actual thesis work? The answer to the first question is quite simply `Who knows.' The second question is a pretty good one. I'm told design projects aren't really thesis work, so I'll just stick around here until I either come up with `thesis work' or get kicked out. In any case, I have a bachelor's degree already so I can work for someone without them feeling guilty about hiring someone without that meaningless sheet of paper.

The two images above show the flexibility of an arbitrary waveform generator. The word "Erithacus" was sent through the UNIX program `banner.' The output was then manipulated by Matlab to build a vector of X and Y coordinates to plot. The resulting coordinates were programmed into the I and Q waveform generators of the board. Finally, the Tek scope is placed into X/Y mode to display the image.

There's loads of things that can be done with this system. That begs the question - ``Who will do them?'' Once again, I have to answer that I don't know.

Top:
Bottom:
Documentation
thesis.ps Thesis submitted to the graduate college.
paper.ps IEEE Transactions on Education paper.
primer.ps Erithacus primer for student use.
paper.ps ECE 363 lab handouts.

Requirements:
  • Interface - The system must interface to a host computer in a portable and reliable manner. The interface should be fairly high speed to allow the transfer of large waveforms for off-line processing. The speed does not need to be enough to facilitate real-time transfer of digitized waveforms.
  • Transmitter - The system must be capable of generating many different types and speeds of digital communications signals. These would include BPSK, QPSK, MSK, FSK, Spread spectrum, and others. The signaling waveforms used should be somewhat arbitrary and quickly programmable.
  • Receiver - The system must have a programmable receiver capable of digitizing I and Q channels or a quadrature system and demodulate these signals in (of course) real-time. For timing-recovery experiments, in particular, the receiver portion should be linked and clocked from the transmitter to allow tight control of the timing error. The receiver must be able to handle speeds up to 1 million symbols per second (for QPSK) so that precise error counts can be made in a reasonable amount of time. (Say 20 seconds)

Interface and

Control:

 Ethernet was chosen as the interface method due to its popularity, low cost, and speed. The speed was found to be adequate to transfer reprogramming messages to the system as well as transfer digitized waveforms from the system. For long waveforms to be processed off-line, a DRAM SIMM is provided in the system to buffer these waveforms before being transferred over the ethernet.

The Motorola 68360 processor was chosen because of its familiarity, availability of inexpensive development tools (namely GCC for UNIX systems), built-in DRAM interface, and built-in ethernet interface. It mates very easily with Motorola's ethernet physical interface chip, and has lots of GPIO pins to program the 3 Xilinx FPGAs on the system.

2 megabytes of FLASH memory are dedicated to the 68360 for boot code, program code, DSP program code, waveforms, FPGA images, etc. Up to 32 megabytes of DRAM can be placed in the one SIMM socket available for OS RAM and buffering RAM.

The 68360 is also given two serial ports, one for RS-232 communications (so the system can emulate a wireless modem), and one for a mouse to be used with the display.

RTEMS (a real-time OS for embedded systems) is the OS that runs on the CPU and provides a nice, capable environment in which to program.

Transmitter:

 The tranmitter has the following silicon:
  • Two 14-bit 100MSPS D/A converters (Harris HI5741).
  • Two 8kx16 dual-port SRAM (Integrated Device Technology IDT7025).
  • One Motorola DSP56302.
  • One Xilinx 4010XL FPGA.
  • One agile clock synthesis section via direct digital synthesis (Analog Devices AD9850).

The receiver is clocked from the agile clock synthesizer capable of synthesizing frequencies up to 42MHz with 0.029 Hz resolution. This allows a wide variety of output symbol rates.

The transmitter is based on wavetable synthesis techniques. Wavetable synthesis has the advantage of being extremely flexible in the choice of waveforms to produce. Coupled with the Xilinx FPGA as a programmable address generation unit (AGU), the synthesizable waveforms vary include AM, FM, BPSK, QPSK, QAM, FSK, Direct Sequence Spread Spectrum, and many others.

Thanks to the programmable AGU, the transmitter is even capable of synthesizing signals with programmed and tightly controlled inter-symbol interference (ISI). Students can build signals with arbitrary cutoff frequencies in MATLAB and generate those signals.

Receiver:

 The receiver has the following silicon:
  • Two 12-bit 10MSPS A/D converters for waveform capture.
  • Four 12-bit D/A converters for "test point" outputs.
  • Two DSP56302's.
  • 32kx24 dual-ported SRAM for shared memory between DSP's.
  • One Xilinx 4028XL FPGA for a variety of possible uses.
  • One agile clock synthesis section (Analog Devices AD9850).

The receiver is clocked either from the transmitter clock (for timing/clock coherence) or from the agile clock synthesizer in the receiver section. This clock synthesizer uses an AD9850 DDS chip. The DDS runs at 125MHz and can synthesize clocks up to 42MHz.

The FPGA is large enough and fast enough to handle demodulation of the full 10MSPS stream when the system is in a lab mode. This means that no timing or clock recovery is necessary. This allows students to change the sampling point to anywhere in the "eye" which allows them to evaluate the effects of poor timing on BER.

The two signal processors can be used when lower rate signals are being sent through and can do more advanced things such as carrier recovery, timing recovery, filtering, etc.

Jake Janovetz - email: janovetz@uiuc.edu